1. Field of the Invention
The present invention relates to a semiconductor device such as a DRAM (Dynamic Random Access Memory) or the like which is required to operate at high speed, and more particularly to a semiconductor device having a capability for adjusting propagation speed variations between terminals thereof.
2. Description of the Related Art
Semiconductor devices such as DRAMs exchange data with an external controller by way of input signal lines including a data signal line, a control signal line, a clock signal line, etc. Therefore, if a skew, which represents the difference between the propagation speeds of input signals between terminals or devices, becomes large, then such semiconductor devices tend to suffer operational drawbacks. In particular, as the speed of operation of semiconductor devices such as DRAMs is becoming higher in recent years, there is a tendency to establish stricter standards for ranges of variations of input terminal capacitances which represent capacitances between input terminals and the ground potential. In view of such a trend, there has been proposed a semiconductor device having a circuit for adjusting an input terminal capacitance as disclosed in Japanese laid-open patent publication No. 2000-31386, for example.
Such a conventional semiconductor device is illustrated in FIG. 1 of the accompanying drawings. As shown in FIG. 1, input terminal capacitance adjusting device 20 is connected by a connection switching aluminum wiring to a line which connects electrostatic-breakdown-prevention input protection resistor 40 connected to input terminal (bonding pad) 10 and internal circuit 30. Input terminal capacitance adjusting device 20 comprises a plurality of MOS-type capacitive elements 21 each comprising a MOS (Metal Oxide Semiconductor) transistor. The conventional semiconductor device illustrated in FIG. 1 adjusts an input terminal capacitance by changing the pattern of the connection switching aluminum wiring to change connections of MOS-type capacitive elements 21.
However, since MOS-type capacitive elements 21 each comprising a MOS transistor have large junction resistances (Rj) which are resistances between itself and the ground potential, a resistive component thereof increases a the time a capacitance is added, resulting in an increase in an input resistance (Ri).
An equivalent circuit of the conventional semiconductor device illustrated in FIG. 1 after it has adjusted the input terminal capacitance is shown in FIG. 2 of the accompanying drawings.
The capacitance between bonding pad 10 and the ground potential is made up of various capacitances including a PAD capacitance of bonding pad 10, an wiring capacitance of the wiring ranging from bonding pad 10 to protection resistance 40, a diffusion layer capacitance of an output transistor, an wiring capacitance of an internal wiring following protection resistance 40, and other capacitances. Junction resistances (Rj) exist between those capacitances and the ground potential.
Input terminal capacitance (Ci) at the input terminal represents the sum of all capacitances (Cj) connected to the input terminal. The propagation speed is affected by not only the input terminal capacitance, but also the magnitudes of junction resistances (Rj) exist between the capacitances and the ground potential. Therefore, some standards established in recent years include not only standards for input terminal capacitance (Ci), but also standards for input resistance (Ri). Input resistance (Ri) is of a value calculated by weighting junction resistances (Rj) based on the magnitudes of capacitances (Cj) connected thereto and adding the weighted junction resistances.
The values of input terminal capacitance (Ci) and input resistance (Ri) have to fall within ranges according to standards that are stricter for higher-speed semiconductor devices.
For example, for RAMBUS (registered trademark) DRAMs (hereinafter referred to as “RDRAMs”), it has been stipulated that variations of input terminal capacitances (Ci) between terminals be equal to or less than 60 fF (femtofarad) and input resistance (Ri) be in the range from 4 to 10 Ω.
The RDRAM is a DRAM according to a RAMBUS interface for carrying out a data transfer process that has been developed by Rambus, Inc., U.S.A., and is capable of high-speed data transmission.
A typical arrangement of a system using RDRAMs is shown in FIG. 3 of the accompanying drawings. In the system, controller (master) 50 having a RAMBUS interface and a plurality of RDRAMs (slaves) 601 through 60n are interconnected by bus wirings called RAMBUS channels. The RAMBUS channels comprise high-speed small-amplitude signal lines connected to a terminal power supply through resistors equivalent to the impedance of transmission lines. High-speed signals include two clock signals which comprise a CTM (Clock To Master) signal as a clock signal supplied to controller 50 and a CFM (Clock From Master) signal as a clock signal returned from controller 50 to RDRAMs 601 through 60n.
Since at most 32 RDRAMs are connected per channel, clock signals are connected to a total of 64 pins TCLK, RCLK. The CFM signal which is input to the endmost RDRAM is connected to the 64th pin.
With the system thus arranged, if input resistance (Ri) is large, then the clock waveform which has initially had an amplitude of 0.8 V is attenuated by input resistance (Ri) of each pin, and has its amplitude reduced when it is input to the endmost RDRAM. For the clock signal is input to the endmost RDRAM to have a sufficient amplitude, input resistance (Ri) at each terminal needs to be reduced. In applications where higher frequencies are involved, input resistance (Ri) needs to be smaller as the amplitude itself is required to be smaller.
From the standpoint of the attenuation of signals, the input resistance should be held to a minimum value. However, if the input resistance is excessively small, then it causes a large overshoot due to the inductance of the package side.
Accordingly, it is necessary that the value of the input resistance be kept in a certain range. According to the present RAMBUS specifications, the input resistance should be held in the range from 4 to 10 Ω as described above.
With the above conventional semiconductor device, because the input terminal capacitance is adjusted using the MOS-type capacitive elements, the input resistance is also changed when the input terminal capacitance is adjusted. To alleviate such a shortcoming, it has been proposed to construct a capacitive component using a comb-shaped wiring pattern for the purpose of adjusting the input terminal capacitance while minimizing any changes in the input resistance, as disclosed in Japanese patent No. 3292175 and Japanese laid-open patent publication No. 62-291213.
An arrangement of a semiconductor device whose capacitive component is constructed using a comb-shaped wiring is shown in FIG. 4 of the accompanying drawings.
As shown in FIG. 4, the semiconductor device has input terminal 10 partly constructed of a comb-shaped wiring having successive cavities and fingers at constant spaced intervals. The semiconductor device also has a GND (ground) wiring having fingers positioned in the respective cavities of the comb-shaped wiring in an interdigitating fashion. Since the GND wiring is connected to the ground potential, capacitive components are constructed by an electrostatic coupling between the comb-shaped wiring and the GNG wiring. The magnitude of the capacitance of input terminal 10 can be adjusted by adjusting the length of the GND wiring.
With the semiconductor device using the above comb-shaped wiring, any production process for changing the capacitance can be minimized because the input terminal capacitance can be adjusting simply by changing the uppermost-level wiring. Furthermore, inasmuch as the capacitive element is formed of only wirings, any resistive component that is increased by adjusting the capacitive element can be reduced, making it possible to adjust the input terminal capacitance while minimizing an increase in the input resistance. In addition, as an inhibitive region around the pad can effectively be utilized, an increase in the area of the circuit for adjusting the input terminal capacitance can be held to a minimum.
However, though the conventional semiconductor device using the above comb-shaped wiring is capable of adjusting input terminal capacitance (Ci), it is unable to adjust input resistance (Ri). Therefore, it has been difficult to satisfy standards for both input terminal capacitance (Ci) and adjust input resistance (Ri).